Jitter-induced power/ground noise in CMOS PLLs: a design perspective

2000

Abstract Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise.

2004

Abstract Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed.

2007 44th ACM/IEEE Design Automation Conference, 2007

Phase-Locked Loops (PLLs) are versatile modules for synchronization and applications such as high-speed serial interfaces in System-on-Chips (SoCs). Their precisions are critical to proper functioning of the SoCs. Intermodule interference such as simultaneous switching noise (SSN) is time-varying, where the stationary assumption in conventional jitter analysis does not apply. We propose a methodology to compute PLL jitter by investigating the harmonic relations between the PLL system with SSN. This provides statistical analysis over many VCO design parameters, SoC modules and noise barrier configurations. Its accuracy and efficiency are compared against circuit simulations.

—This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissi-pation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed. Index Terms—Clock generation, clock multiplier, figure-of-merit (FOM), frequency synthesizer, jitter, low jitter, low noise, phase-locked loop (PLL), phase noise, timing jitter.

Journal of Semiconductors, 2010

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 m CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and-114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.

2006

This paper analyzes phase locked loops (PLLs) from the noise point of view. It is important to now how different noise sources affect the noise performance of the output signal. The sources of noise may be classified into two types, the noise at input, and the noise of VCO. Since a number of performance metrics have to be taken into account simultaneously for the design of low noise PLLs, so the design is very complex because these metrics are not independent of each other. This paper addresses the problem of noise and its reduction to improve the design and operation of PLLs, the simulation results show the effect of the components in both time and frequency domain.

2000

A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with modulated stationary noise models, spectral decomposition of stochastic process and decomposition of noise into orthogonal components i. e. phase and amplitude noise. The method is illustrated by examples of jitter computation in PLLs.

2007

Random jitter (RJ) is a significant noise component in PLL systems that use ring-based oscillators. In order to estimate RJ, accurate modeling of the VCO phase noise is essential. In this paper, the authors will present how the VCO phase noise they obtained from HSPICE RF and from the Impulse-Sensitivity Function (ISF) method compared to lab measurements, the limitations of the two methods and how these phase noise estimates can be used to obtain a prediction of RJ noise component in a PLL.

IEEE Journal of Solid-State Circuits, 1995

Abstruct-A fully integrated phase-locked loop (PLL) in a digital 0.5 um CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than M O O ps with a peak-to-peak jitter of f 5 0 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator.

Solid-State Circuits IEEE International Conference, 1992

The authors describe a phase-locked-loop (PLL)-based deskewed clock generator that is fully integrated with a microprocessor and achieves a skew of less than 0.1 ns with peak-to-peak jitter of 0.45 ns using an 0.8-μm CMOS technology. The block diagram of the deskewed clock generator is shown along with the measured schmoo diagram of the PLL clock generator functionality frequency versus