Ground bounce in digital VLSI circuits

2000

Abstract This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics.

● Signal integrity is a crucial problem in VLSI circuits. ● Package pins, bonding wires, and interconnects cannot be treated as short circuits any more. ● Power/ground bounce limits the performance of high-speed VLSI circuits. ● The noise effects become worse as the clock speed and the number of devices and I/O drivers increase. ... ● Current flowing through the output buffers was modeled as a triangular waveform [Katopis, Proc. IEEE '85]. ... ● The square-law current model was used to model the MOS transistor and the local negative feedback effect was accounted for [ ...

IEEE Journal of Solid-state Circuits, 2004

Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the VDD-VSS admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. This paper addresses (1) the dependence of the VDD-VSS admittance on the different states of the circuit and the interconnect and (2) the computation of total supply current with ground bounce. The VDD-VSS admittances of several test circuits are computed with 13% maximum error relative to the measurements on a test ASIC fabricated in a 0.18µm CMOS process on a high-ohmic substrate with 18Ωcm resistivity. It is also shown that this admittance depends on the connectivity of the gates to the supply rail rather than their connectivity among each other.

1988

di dt d remains relatively constant for the voltage d t d' d t The authors would like to thank J. Nahas for his comments and J. Rowland for testing the device. 88 e 1988 IEEE International Solid-state Circuits Conference

IEEE Transactions on Electromagnetic Compatibility, 2018

2015

Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE mode transition. FinFET based designs are compared with MOSFET based designs on basis of different parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software tool used for simulation and circuit design.

International Journal of Information and Electronics Engineering, 2013

As technology is continuously scaling down leakage current is increasing exponentially. Multi-Threshold CMOS technique is a well known way to reduce leakage current but it gives rise to a new problem i.e. ground bounce noise which reduces the reliability of the circuit and because of this circuit may incorrectly switch to the wrong value or may switch at the wrong time. Ground bouncing noise produced during sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of noise-aware forward body biased multimode MTCMOS circuit techniques to deal with the ground bouncing noise is evaluated in this paper. An additional wait mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by 93.28% and standby leakage current is reduced by 23.94% as compared to standard trimode MTCMOS technique. To evaluate the significance of the proposed multimode Multi-Threshold CMOS technique, the simulation has been performed for 16-bit full adder circuit using BPTM 90nm standard CMOS technology at room temperature with supply voltage of 1V .

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

With technology scaling into the deep sub-micron regime, the power supply and ground noise, which is introduced by the simultaneous switching activity in digital circuits, becomes a challenge for SoC and Networks-on-Chip (NoC) design. In this paper, analytical expressions of the magnitude of ground bounce for different gate switching ratios are derived. It is shown that, by spreading the switching activity, asynchronous circuits design contributes to the ground bounce suppression in two aspects: (1) a significant decrease in the switching current strength and (2) a slight increase in the on-chip intrinsic decoupling capacitance. In order to minimize the switching ratio in large-scale digital VLSI systems, the globally asynchronous locally synchronous (GALS) design is exploited for coarse-grained scheduling and spreading the gate switching over different local clock domains. Important design guidelines, including the GALS system partitioning and local clock modulation, are discussed. As a practical example, a 64-point pipelined SYNC/GALS FFT processor was implemented using the IHP 130-nm CMOS process. The measurements on the packaged chip demonstrate that, compared with the synchronous mode, around 40% reduction in the magnitude of ground bounce is achieved in the GALS mode.

Sub-threshold leakage current is exponentially increased with the scaling down the technology in CMOS circuits. MTCMOS is the method to reduce the leakage current but it arise a problem Ground bouncing noise which degrades the circuit reliability. Ground bouncing noise is important issue in MTCMOS circuits. It produced when circuit is transition from SLEEP to ACTIVE mode. This paper describes the various noise minimization MTCMOS techniques. The comparison of different techniques according to magnitude of Ground bouncing noise is tabulated. Dependency of Ground bouncing noise and power consumption on the various parameters like sleep transistor size, controlling transistor size, Temperature, supply voltage and threshold voltage is also characterized in this paper.

1996

Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-m CMOS test chip have demonstrated that these new buffers generate 2.52 less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current.