Analysis of jitter due to power-supply noise in phase-locked loops

2006

This paper analyzes phase locked loops (PLLs) from the noise point of view. It is important to now how different noise sources affect the noise performance of the output signal. The sources of noise may be classified into two types, the noise at input, and the noise of VCO. Since a number of performance metrics have to be taken into account simultaneously for the design of low noise PLLs, so the design is very complex because these metrics are not independent of each other. This paper addresses the problem of noise and its reduction to improve the design and operation of PLLs, the simulation results show the effect of the components in both time and frequency domain.

2012

– Timing jitter is one of the most significant phaselocked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing of jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3 rd-order PLL. I.

2007

Random jitter (RJ) is a significant noise component in PLL systems that use ring-based oscillators. In order to estimate RJ, accurate modeling of the VCO phase noise is essential. In this paper, the authors will present how the VCO phase noise they obtained from HSPICE RF and from the Impulse-Sensitivity Function (ISF) method compared to lab measurements, the limitations of the two methods and how these phase noise estimates can be used to obtain a prediction of RJ noise component in a PLL.

Journal of Semiconductors, 2010

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 m CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and-114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

It is important to predict noise at the early stages of a top-down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator (VCO), power supply noise, and their effects on the overall phase jitter within a faulty PLL can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally-verified theoretical predictions.

2009 IEEE Custom Integrated Circuits Conference, 2009

Timing jitter is one of the most significant phaselocked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing of jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3 rd-order PLL.

International Journal of Circuit Theory and Applications, 2017

In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18-μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4-mW and minimum 2.6-mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak-to-peak jitter is equal to 5.17 ps, and its minimum peak-to-peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively. KEYWORDS charge pump, delay locked loop, frequency range, jitter, voltage controlled delay line Delay locked loops (DLLs) have first-order control systems. DLLs are similar to phase locked loops (PLLs) in many aspects, and they are being used a lot in microprocessors and memories. DLLs can be used where stability, jitter performance, and occupied chip area are important. The performance of a DLL depends on many assistant parameters including static phase error, lock time, lock range, and jitter. Static phase error is the phase difference between output signal of last stage of VCDL and input reference signal in lock mode. Lock time is the duration in which a DLL reaches stable lock mode with respect to its initial condition. Lock range in DLL is actually the range between minimum and maximum delays in a VCDL, and it directly affects DLL operating frequency range. Lock range can increase in a VCDL through increasing delay cells. In other words, delay range implies frequency range which a DLL can lock. The small and random variations in output signal are called jitter. DLLs show better jitter performance in comparison with PLLs. Nowadays, DLLs with wide frequency range and low power are of high importance in mobile applications. In addition, using frequency synthesizers and multipliers based on DLLs has increased frequency range remarkably. A

2002

Abstract Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-locked-loops are widely used as clock generators of microprocessors.

IEEE Journal of Solid-State Circuits, 1995

Abstruct-A fully integrated phase-locked loop (PLL) in a digital 0.5 um CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than M O O ps with a peak-to-peak jitter of f 5 0 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator.