A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers

A synthesis-based bandwidth enhancement technique for CMOS amplifiers/buffers is presented. It achieves bandwidthenhancement ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93 for passive network with balanced capacitive loads. By employing a step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Time-domain behavior of the proposed technique is examined. Two prototype amplifier/buffer circuits are designed using lower order passive networks to save chip area and circuit complexity. The test chips are fabricated in a 0.18 m CMOS process, and measurements verify the frequency-and time-domain analyses. The amplifier provides 18.5 dB gain and 28 GHz bandwidth, while consuming 52 mW power from a 1.8 V supply.

2003

Abstract This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (eg, crosstalk, power/ground noise). The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter.

2003

Abstract-A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new splitcapacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed. Summarizing, the methodology described in this paper simultaneously considers the interrelated issues of circuit speed, power dissipation, physical area, and system reliability, permitting the efficient design of tapered buffers.

A design of multiplier/divider circuit using a single Current Differencing Buffered Amplifier (CDBA) is presented. Here the objective is to simultaneously realize a multiplier and a divider without changing the circuit configuration which achieves less power consumption. It uses the Trans Linear technique to find out the theoretical output of the circuit. Here the current mode approach is used which is suitable for low voltage high speed analog circuit design. The proposed structure is implemented in 180-nm CMOS technology in cadence virtuoso environment. The power consumption is found to be reduced whose value is 45.67µw and the bandwidth of the designed circuit is found to be improved whose value is 83.6 MHz.It achieves more simplicity and flexibility compared to existing designs and is free from parasitic capacitance.

Analog Integrated Circuits and Signal …, 2003

In this paper, some topologies of novel power-efficient single-ended and fully differential amplifiers and buffers are presented. The reduction of the power dissipation has been ensured through the application of an adaptive biasing architecture which gives a current dependent on the input differential voltage. This allows the minimization of the stand-by power consumption without affecting the transient characteristics. The proposed topology, implemented in a standard CMOS technology, has been applied in the design of input and output stages of low-power amplifiers and voltage buffers, considering them also in the fully differential version. Simulation and measurement results showing good general performance will be also presented.

2009 European Conference on Circuit Theory and Design, 2009

A methodology for designing CMOS inverter-based output buffers considering speed, gain, jitter, and drivability requirements is presented. It adapts the band broadening technique of the classic Cherry-Hooper amplifier to CMOS inverters. A buffer designed this way offers higher speed than a commonly used simple chain of inverters with exponentially increasing gate widths. The buffer is implemented by making minor modifications to a 4-stage CMOS inverter chain. The proposed design is suitable for output buffers for high-speed CMOS logic circuits.

2003

Abstract A comprehensive study of ultra high-speed current-mode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, a new 20GHz regenerative latch circuit will be introduced. Experimental results show a higher performance for the new latch architecture compared to a conventional CML latch circuit at ultra high-frequencies.

A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it is connected with large capacitive load.The increasing width of each inverter in the chain of CMOS inverters is based on tapering factor.The scaling or tapering factor of each stage is dependant on technology used, driving load and the number of stages used.