A Study of High-Frequency Regenerative Frequency Dividers

This paper introduces a nonlinear analysis of tuned regenerative dividers that explores into the transient behavior of the system. Broadly, two such divider implementations have been dealt with, tuned regenerative dividers and injection locked dividers. A detailed nonlinear analysis based on the application of Stroboscopic concept and the first-order perturbation method is used to derive closed-form expressions for start-up condition, output amplitude, maximum operating bandwidth, and frequency spectrum when regenerative dividers go out of "locking" range. Based on the developed theory, design guidelines for high frequency regenerative dividers have been charted out. The results are verified through extensive numerical and SpectreRF simulations of several gigahertz dividers in 0.18-m CMOS technology.

This paper presents a regenerative frequency divider topology that provides two synchronous outputs of 1/N and (N −1)/N times the input frequency. This topology may lead to a saving in chip area and power consumption compared to cascaded divider chains trying to achieve the same division ratio. Design trade-offs are discussed following a theoretical treatment. A proof-of-concept divider with two synchronous outputs at 1/4 and 3/4 of the input frequency is designed in a 0.13 µm CMOS technology. The implemented divider achieves a locking range of 5% around 4 GHz for an input power of 8 dBm and a DC power consumption of 5 mW from a 1 V supply.

This paper presents a theoretical analysis of the maximum frequency of operation of CMOS static frequency dividers. The approach is based on the transient analysis of output voltages derived from differential equations of the large-signal model of the circuit. Tradeoffs and design techniques for very high frequency dividers have been discussed on the basis of the derived expression. An inductor-less 45 GHz divider and a shunt-peaked 60 GHz divider have been designed in 0.13 µm process following the suggested design techniques. Detailed simulation results have been presented.

2010

This paper discussed the circuit level design and simulation of fractional-N frequency divider, a circuit block used mainly in frequency synthesizer. The design was done in schematic level. A low power 0.5 micron CMOS technology called CMOSIS5 used for modeling the circuit devices. The frequency divider was design for 900 MHz GSM standard mobile communication application. For the simulation, circuit level simulator SPICE was used. The circuit was run under 1 GHz input frequency. Simulation results show that the circuit was running well in this frequency input.

IEEE Microwave and Wireless Components Letters, 2000

2004

Abstract In this paper we present the design and analysis of a distributed regenerative frequency divider (DRFD) based on a distributed single-balanced mixer. Artificial transmission lines are incorporated in the distributed single balanced mixer to absorb the parasitic capacitances. The circuit is realized in a 0.18μm standard CMOS process. It shows a division by two for an input frequency of 40GHz, while consuming 10mW from a 1.8 V supply.

IET Circuits, Devices & Systems, 2007

A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-mm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages.

IJIRST, 2014

A low power 1MHz Full programmable frequency divider in 45-nm CMOS process is presented in this paper. The divide ratio can be varied from 2400 to 2431 in a step size of 1.The divider consists of a divide-by-2 circuit, divide-by-2/3 prescaler, divide-by-32/33 prescaler, a programmable pulse-swallow counter. The post simulation results demonstrate that the divider can operate with the input frequency ranging from 2.46GHz-2.541GHz. Measured results show that programmable divider consuming only 613.39 µW at 1V power supply. The programmable frequency divider is design and simulated on Tanner EDA Tool using 45nm CMOS process technology with supply voltage 1 V.

2004

Abstract Frequency dividers play an important role in high speed communications systems. In particular, optical communication circuits demand frequency dividers capable of operating well above 10 GHz. This paper presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz. This circuit is designed and simulated in a standard 0.18 μm CMOS process.

2006 IEEE North-East Workshop on Circuits and Systems, 2006

This paper presents the design of a high-speed wide-band frequency divider. The divider core is formed with a low voltage swing current mode logic (CML) structure, which enables high frequency operation at very low power dissipation. The divider exhibits very wide locking range from 4GHz-41GHz, and it has an input sensitivity of-31dBm at 30GHz. The divider core draws only 750µA from a 1.2V supply. Post layout simulation results in 90-nm CMOS technology are provided.